On Tuesday, April 13th, TSMC hosted it’s annual Technology Symposium at the San Jose Convention Center. Each year, this event seems to grow larger and convey greater amounts of gravitas, and 2010 was no exception.

From breakfast, through the four morning keynotes, the Synopsys-sponsored lunch for 500+ people, the heavily attended breakout sessions in the afternoon, and the late-afternoon reception hosted by Virage Logic – TSMC pulled out all the stops.

Of particular interest were the opening keynotes from TSMC Chairman & CEO Dr. Morris Chang, and Senior Vice President for R&D, Dr. Shang-Yi Chiang.

Both executives emphasized the theme of collaboration – an idea, they said, that TSMC has thoroughly embraced as a means of load sharing today’s semiconductor R&D costs across the industry, as well as streamlining and optimizing the entire supply chain. Per TSMC‘s messaging on April 13th …

* Collaboration boosts differentiation, by distinguishing between private efforts versus community efforts.

* The more efficient the ecosystem, the more time and resources are preserved for innovation by the individual players within that ecosystem.

In other words: Collaboration reduces waste!

But, collaboration requires coordination: TSMC to the rescue!

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Design Platforms and Solutions ...

Coordinating collaboration was on bold display during the 4 PM breakout session at the Symposium, a session lead by TSMC Deputy Director for EDA and Design Service Marketing, Tom Quan, who spent an intense 40 minutes walking his audience through the vast details of TSMC’s muscular roadmap for design enablement and flow.

It was clear from Quan’s presentation and slides that TSMC is moving aggressively to integrate all aspects of the design process, based on a complex set of interrelated structures and features …

* TSMC Modeling Interface [TMI] – with Synopsys, LegendDesign, Mentor Graphics, Cadence, and SimuCAD listed as qualified providers at 40- and 28 nanometers.

* SPICE Qualification Status – with Synopsys, Cadence, Mentor, Magma, Berkeley Design Automation, and SimuCAD qualified at TSMC’s 28-nanometer low power node [N28LPT], or 29-nanometer high performance node [N28HPT], or both – for design kits, tech files, and P&R tech files.

* Substrate Noise Analysis Qualification & iSNA Format – with availability in the second half of 2010 from Cadence, CWS, and Apache.

* TSMC Interoperability Initiative – Quan said, “It’s unfortunate that each proprietary format requires a lot of duplicate effort on the part of the users,” and went on to detail TSMC’s goals (improved data accuracy and integrity and design reuse) and strategies (collaboration with ecosystem partners to validate interoperable data formats).

* TSMC Interoperable Design Kits – include iDRC, iLVS, iRCX, and iPDK to promote “early adoption of TSMC advanced node processes,” as well as “early adoption of qualified tools from qualified EDA vendors,” including Synopsys, Cadence, Mentor Graphics, Magma, SpringSoft, CiraNova, Integrated Software, Ansoft, Apache, Lorentz Solution, and Silicon Frontline.

* Interoperable Place & Route Techfile [iPRT] – anticipates offerings from Cadence, Magma, Synopsys, and Mentor Graphics by mid-to-late 2010.

* TSMC Analog Base Cells [ABC] – includes “a set of frequently-used analog basic cells, optimized aspect ration and layout, and ready integration into analog circuits.”

* AreaTrim Design/Process Co-Optimization – includes TSMC’s “Slim Libraries.”

* Technology Benchmarking Using ARM.

* Comprehensive IP Portfolio – according to Quan’s slides, includes 3000+ IP cores from 40+ IP vendors. By the way, “TSMC’s closest competitor has less than half that number.”

* Integrated Sign-Off Flow [ISF] – based on a “complete production design flow based on TSMC’s usage and tapeout experience.”

* Reference Flow 11.0 – for digital design, includes 28-nanometer enablement, ESL, Interconnect fabric, TSV [through-silicon vias], SiP [that’s IP!], Low Power considerations, Statistical design, and DFM.

* EDA Tool Qualification Report – currently includes AtopTech, Mentor, Apache, Cadence, Magma, and Synopsys at 40-nanometers, but more will be named at 28 nanometers.

* AMS Reference Flow 1.0 – for analog & mixed/signal design, available by Q3 2010, it will include 28-nanometer PLL designs, LDE [Layout Dependent Affects], a front-end to back-end tapeout flow, and of course …

A qualification platform for advanced EDA Tools and Methodologies.

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Pax Romana: And the winner is ...

In the course of his astounding presentation, Tom Quan invoked TSMC-approved tools or TSMC-supplied solutions for ESL, DFM, IP, IP integration, analog and mixed-signal design, digital design, sign-off, tapeout, and even the business model that wraps it all together. The scope of the vision was astonishing.

Clearly TSMC intends to qualify absolutely everything that anybody needs to design chips today. More importantly, if they don’t like what the tool vendors are providing, they’ll do it themselves:

All tool and IP vendors will provide solutions that are interoperable, standardized to the standards that TSMC has established and/or approved. And, by the way, they’ll let you know if and when they’ll be needing the next part in the puzzle.

Yes, efficiency is the goal, collaborative R&D is the goal, saving time and resources is the goal, but ultimately, TSMC calling the shots is the real goal!

And, really – why not? At nanometer geometries, somebody apparently needs to step in and create calm out of the design landscape chaos – particularly in light of the difficulties of manufacturing to the necessary tolerances to create products that work and yields that turn a profit, within a supply chain that’s costly and complex.

Stand down, you squabbling EDA vendors; step aside, you global manufacturing consortia; sit down, you IP and system integration organizations; TSMC has commanded …

A New Pax Romana.

In reality, however, it’s far less profound. TSMC has simply created …

A New IDM.

May 26, 2010

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